1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
To realize miniaturization and high-density mounting of the semiconductor device, a semiconductor package (semiconductor device) in which a plurality of semiconductor elements are stacked and sealed in one package is in practical use. In the semiconductor package (TSOP or the like) using a lead frame, the plurality of semiconductor elements are stacked on the lead frame in order, and electrode pads of the respective semiconductor elements are electrically connected to lead portions of the lead frame via bonding wires (metal wires).
When semiconductor elements are mounted on a single surface of the lead frame, a lead frame which has been subjected to depress process so that its element mounting portion is lower than the lead portion is used in order to increase the number of semiconductor elements to be mounted. The depress process is a factor of increasing the manufacturing cost of the lead frame and thus the manufacturing cost of the semiconductor package. Further, the depress-processed lead frame has an inclined portion and therefore has a limit in size of the mountable semiconductor element.
It has also been considered to mount a plurality of semiconductor elements stacked respectively on both surfaces of the lead frame (see JP-A 2007-035865 (KOKAI)). In this case, the semiconductor elements are resin-molded while mounted on both surfaces of the lead frame, so that the filling performance of the sealing resin deteriorates depending on the arrangement of the pads of the semiconductor elements and on the shape of the lead frame associated with the arrangement. In terms of the above points, it is desired to mount the semiconductor elements stacked in multiple tiers only on a single surface of the lead frame. However, a conventional semiconductor device employing the single-surface stack structure has a problem such as an increase in manufacturing cost due to the depress process or a limit in element size or the like.
Further, since the arrangement order of the inner leads of the lead frame basically corresponds to that of the outer leads, the lead frame can cope with limited circuits. More specifically, since the lead frame is fabricated by forming lead patterns on one metal plate, the inner leads cannot be made cross each other. When bonding wires are made cross each other, the bonding wires can come into contact with each other to short out. Accordingly, it is impossible to make the arrangement order of the electrode pads of the semiconductor element different from that of the outer leads.
To such a point, a lead frame in which between a die pad portion and an inner lead, a relay conductor electrically insulated from them is provided is described in JP-A 2000-077595 (KOKAI). When a lead frame in which a re-wiring conductor is disposed separately from the inner lead is used, an increase in package size is unavoidable. Since the element size and the package size become close to each other accompanying the increase in size of the semiconductor, it is demanded to suppress the increase in package size while coping with various circuits by the lead frame.